In a multi-phase DC-DC power converter, balance between currents in all phases needs to be considered. Imbalance in output current between phases can cause uneven heat distribution, which adversely affects performance, power efficiency, and size of the power converter. It must be recognized that pulse-width modulation (PWM) control of multiple continuous conduction-mode (CCM) power converters configured to share a common load will not necessarily achieve sharing the output current equally between these converters. A consideration should be taken in the control method to achieve the current balance between phases.
Ripple-based constant ON time (COT) converters have been popular for their exceptionally fast response to load transients, inherent control simplicity and stability. Numerous schemes have been proposed for achieving output current balance between phases by altering the ON time of a phase in proportion with the deviation of its current from the average of all phases. FIG. 1 depicts an example of such a prior-art COT converter, wherein the inductor current of each of N converter cells 11, IL1˜ILN, is monitored by a current sense circuit 101 and compared by an imbalance detector circuit 105 to an average current of all N phases derived by the averaging circuit 102 after passing low-pass filters 103. The resulting imbalance voltage, ΔVCS1˜ΔVCSN, is subtracted from a ramp threshold voltage VO(est) of an ON time generator 107 at a summing node 106. The threshold voltage VO(est) is typically generated in proportion with the output voltage VO, whether actual, or estimated, and the ramp current is generated in proportion with the input voltage VIN of the power converter to maintain constant switching period Ts at all operating conditions.
Another scheme includes altering the TON signal in each individual phase in proportion with the imbalance signal.
Due to the presence of significant switching ripple component in the inductor current, low-pass filters 103 are required to achieve current balancing. These filters affect the current balancing loop dynamics and, therefore, degrade the load transient response.